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RFD14N05L, RFD14N05LSM, RFP14N05L
Data Sheet January 2002
14A, 50V, 0.100 Ohm, Logic Level, N-Channel Power MOSFETs
These are N-channel power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers and relay drivers. This performance is accomplished through a special gate oxide design which provides full rated conductance at gate bias in the 3V-5V range, thereby facilitating true on-off power control directly from logic level (5V) integrated circuits. Formerly developmental type TA09870.
Features
* 14A, 50V * rDS(ON) = 0.100 * Temperature Compensating PSPICE(R) Model * Can be Driven Directly from CMOS, NMOS, and TTL Circuits * Peak Current vs Pulse Width Curve * UIS Rating Curve * 175oC Operating Temperature * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards"
Ordering Information
PART NUMBER RFD14N05L RFD14N05LSM RFP14N05L PACKAGE TO-251AA TO-252AA TO-220AB BRAND 14N05L 14N05L FP14N05L
Symbol
D
G
NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-252AA variant in the tape and reel, i.e., RFD14N05LSM9A.
S
Packaging
JEDEC TO-251AA
SOURCE DRAIN GATE DRAIN (FLANGE)
JEDEC TO-252AA
DRAIN (FLANGE) GATE SOURCE
JEDEC TO-220AB
SOURCE DRAIN GATE DRAIN (FLANGE)
(c)2002 Fairchild Semiconductor Corporation
RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B
RFD14N05L, RFD14N05LSM, RFP14N05L
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified RFD14N05L, RFD14N05LSM, RFP14N05L 50 50 10 14 Refer to Peak Current Curve Refer to UIS Curve 48 0.32 -55 to 175 300 260 UNITS V V V A
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg
W W/oC oC
oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 150oC.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS IGSS rDS(ON) t(ON) td(ON) tr td(OFF) tf t(OFF) Qg(TOT) Qg(5) Qg(TH) CISS COSS CRSS RJC RJA RJA TO-251 and TO-252 TO-220 VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDS = 25V, VGS = 0V, f = 1MHz Figure 14 VDD = 40V, ID = 14A, RL = 2.86 Figures 20, 21 TEST CONDITIONS ID = 250A, VGS = 0V, Figure 13 VGS = VDS, ID = 250A, Figure12 VDS = 40V, VGS = 0V VDS = 40V, VGS = 0V, TC = 150oC VGS = 10V ID = 14A, VGS = 5V, Figures 9, 11 VDD = 25V, ID = 7A, RL = 3.57, VGS = 5V, RGS = 0.6 MIN 50 1 TYP 13 24 42 16 670 185 50 MAX 2 1 50 100 0.100 60 100 40 25 1.5 3.125 100 80 UNITS V V A A nA ns ns ns ns ns ns nC nC nC pF pF pF
oC/W oC/W oC/W
Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 5V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage (Note 2) Diode Reverse Recovery Time NOTES: 2. Pulse Test: Pulse Width 300ms, Duty Cycle 2%. 3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current Capability Curve (Figure 5).
(c)2002 Fairchild Semiconductor Corporation RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B
SYMBOL VSD trr ISD = 14A
TEST CONDITIONS
MIN -
TYP -
MAX 1.5 125
UNITS V ns
ISD = 14A, dISD/dt = 100A/s
RFD14N05L, RFD14N05LSM, RFP14N05L Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 0 25 125 50 75 100 TC , CASE TEMPERATURE (oC) 150 175 12 0.8 0.6 0.4 0.2 0
Unless Otherwise Specified
16
8
4
0 25 50 75 100 125 TC, CASE TEMPERATURE (oC) 150 175
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE
2 1 THERMAL IMPEDANCE ZJC, NORMALIZED 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 10-5 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-2 10-1 10-3 t, RECTANGULAR PULSE DURATION (s) 100 101
PDM
10-4
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
100
IDM, PEAK CURRENT CAPABILITY (A)
TC = 25oC TJ = MAX. RATED
200 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 100
FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I
ID, DRAIN CURRENT (A)
= I25
100s 10 1ms 10ms 100ms DC 100
175 - TC 150
1 0.5 1
OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10 VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 5V TC = 25oC 10 -5 10-4 10 VGS = 10V 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
(c)2002 Fairchild Semiconductor Corporation
RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B
RFD14N05L, RFD14N05LSM, RFP14N05L Typical Performance Curves
50 IAS, AVALANCHE CURRENT (A)
Unless Otherwise Specified (Continued)
35 30 ID, DRAIN CURRENT (A) 25 20 15 10 5 0 VGS = 3V VGS = 2.5V 0 1.5 6.0 3.0 4.5 VDS, DRAIN TO SOURCE VOLTAGE (V) 7.5 PULSE DURATION = 80s, TC = 25oC DUTY CYCLE = 0.5% MAX.
VGS = 10V
VGS = 5V VGS = 4.5V VGS = 4V
STARTING TJ = 25oC 10
STARTING TJ = 150oC If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) 1 If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1] 0.01 0.1 1 tAV , TIME IN AVALANCHE (ms) 10
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS
IDS(ON), DRAIN TO SOURCE CURRENT (A)
35 -55oC 175oC rDS(ON) , DRAIN TO SOURCE ON RESISTANCE (m) 30 25 20 15 10 5 0 0 1.5 3.0 4.5 6.0 VGS, GATE TO SOURCE VOLTAGE (V) 7.5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. VDD = 15V 25oC
250 ID = 7A 200 ID = 14A ID = 28A
150
100
ID = 3.5A
50 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. 0 2.5 3.0 3.5 4.0 4.5 VGS , GATE TO SOURCE VOLTAGE (V) 5.0
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
160 140 SWITCHING TIME (ns) 120 100 80
VDD = 25V, ID = 14A, RL = 3.57
2.5 td(OFF) NORMALIZED DRAIN TO SOURCE ON RESISTANCE 2.0
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. VGS = 10V, ID = 14A
tr tf
1.5
60 40 td(ON) 20 0 0 20 30 40 10 RGS , GATE TO SOURCE RESISTANCE () 50
1.0
0.5
0 -80
-40
0 40 80 120 TJ, JUNCTION TEMPERATURE (oC)
160
200
FIGURE 10. SWITCHING TIME vs GATE RESISTANCE
FIGURE 11. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
(c)2002 Fairchild Semiconductor Corporation
RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B
RFD14N05L, RFD14N05LSM, RFP14N05L Typical Performance Curves
2.0 VGS = VDS, ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE
Unless Otherwise Specified (Continued)
2.0 ID = 250A
NORMALIZED GATE THRESHOLD VOLTAGE
1.5
1.5
1.0
1.0
0.5
0.5
0 -80
-40
0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
200
0 -80
-40
0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC)
200
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
800 CISS C, CAPACITANCE (pF) 600 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD COSS 200 CRSS 0 0 5 10 15 20 VDS , DRAIN TO SOURCE VOLTAGE (V) 25
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
50 VDD = BVDSS VDD = BVDSS 5 VGS , GATE TO SOURCE VOLTAGE (V)
VDS , DRAIN TO SOURCE VOLTAGE (V)
40
4
30
3
400
20
10
0.75 BVDSS 0.50 BVDSS 0.25 BVDSS RL = 3.57 IG(REF) = 0.4mA VGS = 5V I G ( REF ) 20 -----------------------I G ( ACT ) t, TIME (s) I G ( REF ) 80 -----------------------I G ( ACT )
2
1
0
0
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260, FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 15. TRANSCONDUCTANCE vs DRAIN CURRENT
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
(c)2002 Fairchild Semiconductor Corporation
RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B
RFD14N05L, RFD14N05LSM, RFP14N05L Test Circuits and Waveforms
(Continued)
tON VDS VDS VGS RL
+
tOFF td(OFF) tr tf 90%
td(ON)
90%
DUT RGS VGS
-
VDD
0
10% 90%
10%
VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
VDS RL VDD VDS VGS = 10V VGS
+
Qg(TOT)
Qg(5) VDD VGS VGS = 1V 0 Qg(TH) IG(REF) 0 VGS = 5V
DUT IG(REF)
FIGURE 20. GATE CHARGE TEST CIRCUIT
FIGURE 21. GATE CHARGE WAVEFORMS
(c)2002 Fairchild Semiconductor Corporation
RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B
RFD14N05L, RFD14N05LSM, RFP14N05L PSPICE Electrical Model
.SUBCKT RFP14N05L 2 1 3 ;
CA 12 8 1.464e-9 CB 15 14 1.64e-9 CIN 6 8 6.17e-10 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 65.35 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 5.68e-9 LSOURCE 3 7 5.35e-9 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01
12 GATE 1 9
rev 9/15/94
DPLCAP 10
5 LDRAIN RSCL1
DRAIN 2
RSCL2
+ 51 5 51 ESCL 50
DBREAK
ESG + EVTO 20 + 18 8
6 8 VTO 6 +
11 EBREAK 17 18 MOS2
RDRAIN 16 21 MOS1 RIN CIN 8
+
DBODY
LGATE RGATE
RSOURCE
7
LSOURCE 3 SOURCE
S1A 13 8 S1B CA + EGS 6 8 14 13
S2A 15 S2B 13 + 14 EDS 5 8 CB IT RBREAK 17 18 RVTO 19 VBAT +
RBREAK 17 18 RBKMOD 1 RDRAIN 50 16 RDSMOD 33.1e-3 RGATE 9 20 5.85 RIN 6 8 1e9 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RDSMOD 14.3e-3 RVTO 18 19 RVTOMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
VBAT 8 19 DC 1 VTO 21 6 0.485 ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/46,7))} .MODEL DBDMOD D (IS = 2.23e-13 RS = 1.15e-2 TRS1 = 1.64e-3 TRS2 = 7.89e-6 CJO = 6.83e-10 TT = 3.68e-8) .MODEL DBKMOD D (RS = 3.8e-1 TRS1 = 1.89e-3 TRS2 = 1.13e-5) .MODEL DPLCAPMOD D (CJO = 25.7e-11 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 1.935 KP = 18.89 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 7.18e-4 TC2 = 1.53e-6) .MODEL RDSMOD RES (TC1 = 4.45e-3 TC2 = 2.9e-5) .MODEL RSCLMOD RES (TC1 = 2.8e-3 TC2 = 6.0e-6) .MODEL RVTOMOD RES (TC1 = -1.7e-3 TC2 = -2.0e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.55 VOFF= -1.55) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.55 VOFF= -3.55) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.55 VOFF= 2.45) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.45 VOFF= -2.55) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; authored by William J. Hepp and C. Frank Wheatley.
(c)2002 Fairchild Semiconductor Corporation
RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM
DISCLAIMER
FAST (R) FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM
OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench (R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER (R)
SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET (R)
VCXTM
STAR*POWER is used under license
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. H4

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